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| AP4410M Advanced Power Electronics Corp. Low On-Resistance Fast Switching Simple Drive Requirement D D D D N-CHANNEL ENHANCEMENT MODE POWER MOSFET BVDSS RDS(ON) G 30V 13.5m 10A ID SO-8 S S S Description DD The Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. G G The SO-8 package is universally preferred for all commercial-industrial surface mount applications and suited for low voltage applications such as DC/DC converters. SS Absolute Maximum Ratings Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current 1 3 3 Rating 30 25 10 8 50 2.5 0.02 -55 to 150 -55 to 150 Units V V A A A W W/ Continuous Drain Current Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient 3 Value Max. 50 Unit /W Data and specifications subject to change without notice 200606032 AP4410M Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance2 Test Conditions VGS=0V, ID=250uA Min. 30 1 - Typ. 0.037 Max. Units 13.5 22 3 1 25 100 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) VGS=10V, ID=10A VGS=4.5V, ID=5A 20 13.5 4 7 14 16 21 15 1160 240 165 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=15V, ID=10A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS= 25V ID=10A VDS=15V VGS=5V VDS=25V ID=1A RG=3.3,VGS=5V RD=25 VGS=0V VDS=15V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 Test Conditions IS=2.1A, VGS=0V IS=5A, VGS=0V, dI/dt=100A/s Min. - Typ. 17.1 12 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 125 /W when mounted on Min. copper pad. AP4410M 200 150 T A =25 o C 150 10V 8.0V T A =150 o C 10V 8.0V ID , Drain Current (A) ID , Drain Current (A) 100 6.0V 100 6.0V 50 50 V G =4.0V V G =4.0V 0 0 1 2 3 4 5 6 7 8 0 0 2 4 6 8 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 20 1.8 I D =10A 18 T A =25 o C Normalized RDS(ON) 1.6 I D =10A V G =10V 1.4 RDS(ON) (m ) 16 1.2 14 1 12 0.8 10 3 4 5 6 7 8 9 10 11 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 3 100.00 10.00 2 1.00 VGS(th) (V) 1 0 -50 T j =150 o C IS(A) T j =25 o C 0.10 0.01 0 0.4 0.8 1.2 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Jujnction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature AP4410M 12 10000 f=1.0MHz VGS , Gate to Source Voltage (V) 10 I D =10A V DS =15V 1000 8 Ciss 6 C (pF) Coss Crss 100 4 2 0 0 5 10 15 20 25 30 10 1 6 11 16 21 26 31 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 100us 10 Normalized Thermal Response (Rthja) DUTY=0.5 0.2 1ms ID (A) 10ms 1 0.1 0.1 0.05 0.02 0.01 100ms 1s 0.1 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + T a Rthja=125 oC/W T A =25 o C Single Pulse 0.01 DC 0.001 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Circuit Fig 12. Gate Charge Circuit |
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